What is ramp generator

How to Build a Ramp Generator with Transistors

In this project, we will show how to build a ramp generator circuit using transistors and a few other simple components, resistors and a capacitor.

This circuit requires no integrated chips.

A ramp generator is a signal generator which generates a ramp waveform. This waveform increases steadly as the capacitor is being charged until it hits its peak and then decreases even more dramatically as the capacitor is discharged.

Being that this waveform repeats over and over again, this generator can be seen as an oscillator.

If you connect to an output device such as an LED, it will turn the LED first with low brightness and as the amplitude of the ramp increases, the LED will get brighter. As the ramp hits its peak and starts to descend in amplitude, the LED fades out until it turns off. The process then repeats itself over and over again.

The details of how to build this circuit and how exactly it works is described in detail below.

If you have an oscilloscope, you can check the output waveform that the circuit produces. If you do not have an oscilloscope, then you can simply connect to an output device such as an LED to see the fade in, fade out process.

• 2 2N3906 PNP Transistors
• 2N3904 NPN Transistor
• 4 10KΩ Resistors
• 1KΩ Resistor
• 10nF ceramic capacitor

So in this circuit we use 2 PNP transistors and 1 NPN transistor.

Although we’ve designated to use the 2N3906 as the PNP transistor and the 2N3904 as the NPN transistor, you really could use any other type of PNP and NPN transistor that you have. It doesn’t have to be these.

The datasheet for the 2N3906 PNP transistor is found here: 2N3906 PNP Transistor Datasheet.

The datasheet for the 2N3904 NPNP transistor is found here: 2N3904 NPN Transistor Datasheet.

Even though the transistors operate different, from a back view of the transistor, right side up (with the terminal legs of the transistor pointing downward), from left to right, the terminals of the transistor are EBC: Emitter, Base, and Collector.

So when connecting the transistors, this information is needed.

Ramp Generator Circuit Built with Transistors

The ramp generator circuit we will build with transistors and a capacitor and resistors is shown below.

Below is the breadboard version of the above circuit so that you can see the exact wiring of the circuit on a breadboard.

For this circuit, we are using 5VDC.

All the way to the left of the circuit, are a 1KΩ resistor and a 10KΩ resistor in parallel. These resistors in parallel set up a bias voltage for the PNP transistor. This allows for the PNP transistor to turn up and allows current flow from the emitter to the collector of the PNP transistor. The current flowing through this transistor is about 30 microamperes. This is the same current that gets dumped into the 10nF ceramic capacitor, charging it up. This forms the rising edge of the ramp waveform. As the capacitor charges up more and more and the charge gets larger and larger, the ramp on the waveform steadily rises.

Once the voltage rises to a level high enough on the capacitor that turns on the PNP transistor that it is connected to the anode the ceramic capacitor, then the capacitor begins discharging. Think of it this way. When there is no power to the circuit, no current can flow because there is no power. Once we turn on the power, the first PNP transistor (to the leftmost part of the circuit) acts as a current source for the capacitor. The capacitor gets charged up by the PNP current source. As it gets charged, the voltage across the capacitor increases. Know that the voltage across a capacitor is proportional to the amount of current that charges it up. As the current flows into the capacitor, its voltage increases. Once the voltage reaches a certain threshold, the peak of the ramp waveform, it is high enough to turn on the second PNP transistor. Once it turns on the PNP transistor, this PNP transistor turns on the NPN transistor. Both transistors are now operating in saturation mode and are fully conducting. Being that the voltage at the capacitor is now high enough to turn on the transistor, the transistor goes from cutoff (not conducting) to saturation (fully conducting). Now that current can flow through the transistor, the capacitor discharges its current through the transistor. Once all the charge from the capacitor has been discharged from the capacitor, then there is not enough voltage to turn on the PNP transistor. Therefore, the 2 rightmost transistors no longer conduct current. The process starts over with the leftmost transistor, the current source, charging up the capacitor again.

This creates the constant ramp waveform of charging and discharging of the capacitor.

The 2 10KΩ resistors in parallel form a voltage divider. Since the voltage supply is 5V, it divides the voltage in half at the midpoint between the 2 resistors, creating 4.5V of power. This voltage is the bias voltage necessary for the collector of the NPN transistor and the base of the PNP transistor. This voltage is needed so that both transistors can turn on. Know that bipolar junction transistors (BJTs) always need biasing to the base of the collectors in order to operate. With the 4.5 V, biasing power is provided to the base of the first transistor and the collector of the second transistor. However, in order to turn on the first transistor, sufficient positive voltage is needed at the collector of the first transistor. This only occurs when the voltage of the capacitor reaches a certain threshold.

So this is a basic ramp generator built using transistors, resistors, and a capacitor.

There are variations of this circuit which can be done.

If you use a larger-sized capacitor, this would increase the time period of the signal. This is because with a larger capacitor, more charge can be held across the terminals. So since more charge can be held, it takes a longer time to charge up. Therefore, the ramp is longer. In the same way that a greater charge is held across the terminals, it takes a longer time to discharge this capacitor, since it stores more charge. So the incline and decline of the ramp are longer, making for a longer period and decreased frequency.

So the capacitor definitely affects the frequency of the signal. So if you try a larger capacitor such as a 100nF capacitor or a 1μF capacitor, you’ll definitely see a decreased frequency. The same thing applies in reverse, decreasing the value of the capacitor increases the frequency. So if you use a 1nF capacitor, you’ll see an increased frequency.

Another variation you could use is to adjust the amplitude of the supply voltage. By increasing the supply voltage, we increase the amplitude, and, thus, the peak of the ramp waveform. When we increase the voltage, the capacitor can now charge up to a higher voltage. So if we increase the 5V we are currently using to, say, 12V, you’ll see that the amplitude of the signal rises. In the same way, if we decrease the supply voltage, the amplitude and, thus, peak of the signal decreases.

So these are variations we can do is to adjust either the frequency or amplitude of the ramp waveform.

To see how this circuit works in real life, see the video below.

Источник

What is a linear ramp generator?

ANSWER

Unsourced material may be challenged and removed. In electronics and electrical engineering, a ramp generator is a circuit that creates a linear rising or falling output with respect to time. The output variable is usually voltage, although current ramps can be created. Linear ramp generators are also known as sweep generators

How to Build a Ramp Generator with Transistors?

A ramp generator is a signal generator which generates a ramp waveform. This waveform increases steadly as the capacitor is being charged until it hits its peak and then decreases even more dramatically as the capacitor is discharged. Being that this waveform repeats over and over again, this generator can be seen as an oscillator.

What would be the simplest BJT based *linear* ramp generator? Let’s say I have a 74LS161 based counter, and I want an analog ramp generator which will linearly increase until the ripple-carry-output goes back down (so that the ramp goes up the entire time the counter counts, and at 0 it starts over. Trying to avoid yet another chip and I need all the counter bits to count on the up-slope.

Transistor-Based Ramp Generator? a ramp generator from a current source. We show two implementations that both use a PNP current source. Contents 1 Introduction 1 2 Transistor Top Regulation 2 Resistor-Biased Ramp Generator . . . . . . 3 Diode-Biased Ramp Generator . . . . . . . 4 A Parts 5 1 Introduction Our goal is to build a ramp generator like 10V 0V Reset

Precision linear ramp function generator (Patent) DOE ?

A ramp function generator is provided which produces a precise linear ramp unction which is repeatable and highly stable. A derivative feedback loop is used to stabilize the output of an integrator in the forward loop and control the ramp rate.

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Источник

Ramp Generator

Ramp generators are also used in magnetically deflected CRT display systems to generate deflection-coil currents.

Related terms:

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Converters

Hank Zumbahlen , with the engineering staff of Analog Devices , in Linear Circuit Design Handbook , 2008

Ramp Run-Up ADCs

In the ramp run-up architecture shown in Figure 6-72 , a ramp generator is started at the beginning of the conversion cycle. The counter then measures the time required for the ramp voltage to equal the analog input voltage. The counter output is therefore proportional to the value of the analog input. In an alternate version (shown dotted in Figure 6-72 ), the ramp voltage generator is replaced by a DAC which is driven by the counter output. The advantage of using the ramp is that the ADC is always monotonic, whereas overall monotonicity is determined by the DAC when it is used as a substitute.

Figure 6-72: . Ramp run-up ADC

The accuracy of the ramp run-up ADC depends on the accuracy of the ramp generator (or the DAC) as well as the oscillator.

Signal-Processing Circuits

11.10 Ramp and Sweep Generators

Oscilloscope time-base systems consist of a trigger generator followed by a sweep generator. The sweep generator is a gated ramp or sawtooth generator that drives the horizontal deflection amplifier. Ramp generators are also used in magnetically deflected CRT display systems to generate deflection-coil currents. Pulse-width modulators also require sawtooth ramps.

A bootstrap ramp generator ( Fig. 11.50 ) uses the bootstrapping technique to maintain a constant voltage across a timing resistor R. As C charges, the top end of R follows it, driven by the buffer. The result is a linear ramp output. With floating voltage source V, the ramp slope is

FIG. 11.50 . Bootstrap ramp generator.

This perfect scheme is spoiled by shunt resistance R_i (due to the capacitor and buffer input), buffer output resistance R_o, and buffer gain deviation from unity. Let V be gated on at t = 0 as

Then solving the circuit in s, we get

where K is the buffer voltage gain. The bootstrap effect appears as the increase in effective resistance of R + R_o by 1/(1 − K). This increases the time constant by the same factor; in effect, the ramp is generated as the initial segment of a long exponential curve. K, R_o, and R_i all contribute to the time-constant deviation from RC.

Another approach to ramp generation is to use an op-amp integrator. This Miller ramp generator ( Fig. 11.51 ) has a transfer function of

FIG. 11.51 . Miller ramp generator.

For an op-amp, K→∞, and the transfer function approaches −1/sRC, an ideal integrator. With finite gain, the output is an exponential with time constant multiplied by (1 + K); the early part of the curve is approximately linear. The fractional deviation from linear response is

where τ is the effective time constant. Equation (11.169) was derived by series-expanding the response exponential to the quadratic term, subtracting the (ideal) linear and constant terms, and dividing by the linear term. Error grows with time as the exponential becomes increasingly sublinear. This error formula applies to both bootstrap and Miller ramp generators since the responses of both are exponentials.

Finite gain also causes a slope error in the Miller integrator. In (11.168) , let V(s) be that of (11.166) . Then (11.168) corresponds to the normalized time-domain response of

Applying the initial value theorem gives

The initial slope of the ideal ramp response, − 1/sRC, is −1/RC. Thus,

Fast Miller ramp generators are driven by an input current source instead of a voltage source and R. This produces a more linear response and reduces the effect of input impedance. The ideal response of −1/sC is only approximate. More precisely,

The ideal response is multiplied by the s-domain equivalent of the fractional slope error. To approach the ideal, the op-amp must maintain high gain at high frequencies. This is a major limitation, especially since the op-amp output impedance gyrates inductively. For

The op-amp adds an additional pole at its unit-gain frequency f_T.

An improved ramp generator is based on the simplicity of a gated current source charging a capacitor, followed by a buffer amplifier. Feedback loops are avoided, and the step response is faster than for the previous two schemes. Bruce Hofer has recognized the topological equivalence of this current-source ramp generator with the Miller generator, compared in Fig. 11.52 . The difference is in where the ground is put. In the Miller, the BJT is a CE; in the current-source, a CC. In the Miller, any anomalous switching voltage at the FET gate is coupled through C to the output; in the current-source, it is bypassed by C to ground.

FIG. 11.52 . Topological equivalence of Miller generator (a) and current-source ramp generator (b).

Digital-to-Analog and Analog-to-Digital Conversion

David L. Terrell , in Op Amps (Second Edition) , 1996

8.6 DUAL-SLOPE A/D CONVERSION

Figure 8.13 shows the schematic diagram of a basic dual-slope A/D converter. Let us first examine each of its subcircuits and then analyze the overall operation of the circuit.

FIGURE 8.13 . A basic dual-slope analog-to-digital converter circuit.

The heart of the circuit is an op amp, linear ramp generator circuit. Figure 8.14 shows the ramp generator isolated from the rest of the converter circuit. It is designed such that the charging current for capacitor C will always be constant. Basic circuit theory tells us that a constant charging current through a capacitor produces a linear ramp of voltage.

FIGURE 8.14 . The linear ramp generator portion of the circuit shown in Figure 8.13 .

To understand the operation of the ramp generator circuit, let us assume that the capacitor is initially discharged (i.e., 0 volts). This is the purpose of transistor Q₁—as long as it is saturated, capacitor C cannot accumulate a charge. Although the actual saturation voltage of Q₁ may be a few millivolts, let us assume it is truly 0 volts for simplicity. Let us further assume (as an example) that the input voltage to the ramp generator is +5 volts. Now let us cut off transistor Q₁ and allow capacitor C to begin charging. We will compute the current through the capacitor at several times.

At the first instant after Q₁ is cut off, the capacitor has 0 volts of charge. Ohm’s Law tells us that resistor R₁ will have a current of

The op amp is essentially a noninverting amplifier with respect to the capacitor voltage. The voltage gain is given by our basic equation for noninverting amplifiers.

The output voltage at this instant will be 0 volts (i.e, 0 × 2). Resistor R₂ will have 0 volts on both ends, which means it has no current flow through it. We know that negligible current flows in or out of the (+) terminal of the op amp. Now, since 2.5 milliamperes of current is flowing through R₁, but no current flows to the op amp or through R₂, we can apply Kirchhoff’s Current Law to conclude that the entire 2.5 milliamperes must be flowing into capacitor C as a charging current. The direction of the electron current is from ground, up through capacitor C, and through R₁ to the positive 5-volt source. This establishes the initial slope of the charge on C. If we can maintain a constant current, we will maintain a linear slope across C.

Now let us examine the circuit condition after capacitor C has accumulated 1 volt of charge (positive on top). The current through R₁ can now be computed as

With 1 volt on the capacitor and a voltage gain of 2, we can compute the output voltage of the op amp as

The current through R₂ can be found with Ohm’s Law, since it has 1 volt on the left end and 2 volts on the right end.

Again, Kirchhoff’s Current Law will let us conclude that if 2 milliamperes are flowing to the left through R₁ and 0.5 milliampere is flowing to the right through R₂, then capacitor C must still be charging with a 2.5-milliampere current. Let us examine the circuit at one more point.

Suppose we let capacitor C accumulate a charge of 4 volts. The current through R₁ will then be

With +4 volts on the capacitor, the output voltage of the op amp must be

The current through R₂ can be calculated as

Finally, we apply Kirchhoff’s Current Law to show that with 0.5 milliampere flowing right to left through R₁ and 2 milliamperes flowing left to right through R₂, there must surely be 2.5 milliamperes flowing upward through capacitor C. Since the current through capacitor C has remained constant at 2.5 milliamperes, we know that the voltage across it will be a linearly rising ramp. The slope of the ramp is given by the basic capacitor charge equation:

For the present case, the slope of the ramp across C is computed as

The output of the op amp will have a slope that is linear but twice as great, since the amplifier has a voltage gain of 2. In either case, the slope of the ramp is determined by the charging current of C, which is determined by the value of input voltage.

Now, let us analyze the overall operation of the dual-ramp A/D converter shown in Figure 8.13 . The input voltage to the ramp is switch-selected as either the analog voltage to be converted (positive) or a fixed, negative reference voltage. Recall that the input voltage to the ramp circuit determines the slope of the ramp. The position of the analog switch is controlled by the state of the most significant bit (MSB) of a counter. More specifically, if the MSB is low, then the switch will connect the analog input to the ramp generator. If the MSB of the counter is high, then the switch connects the negative reference voltage to the ramp generator input.

The counter is enabled (i.e., allowed to count) as long as the output of the ramp generator is positive. That is, as long as the ramp is above ground, the output of the comparator will be low and will enable the counter. If the ramp ever goes below ground, then the output of the comparator will switch to a high state and disable the counter.

The control circuit provides the overall timing of circuit operation. On receipt of a start conversion signal from the main control system (generally a microprocessor), the control unit will reset the counter to 0 and release (i.e., cut off) Q₁. With the counter reset, the MSB will be 0 and the analog switch will be connecting the analog input to the ramp generator circuit. As the counter counts up, the capacitor voltage (and the op amp output) will be linearly ramping up in a positive direction. This action is indicated in Figure 8.15 as t₁.

FIGURE 8.15 . The positive slope of a dual-slope converter is determined by the value of analog input voltage. The slope of the negative ramp is determined by V_REF.

This action will continue until the counter reaches one-half of its maximum count. At this point, the MSB of the counter will go high and cause the analog switch to move to the reference voltage position. With a negative input voltage applied to the ramp generator, the capacitor will begin to discharge. The discharge will be linear, and the rate will be determined by the value of the negative reference voltage. Eventually, the decreasing ramp will pass through 0 volts, causing the comparator to switch states and disabling the counter. The control circuit senses this event and generates the conversion complete signal, which means that the digital result in the counter is now a valid representation of the analog input voltage.

We know that the initial slope (during time t₁ in Figure 8.15 ) is determined by the value of the analog input voltage. The length of time for t₁, however, is fixed and determined by the speed of the clock and the number of bits in the counter. Time t₂ in Figure 8.15 is the amount of time required for the capacitor to linearly discharge to 0 volts. The slope of t₂ is fixed and is determined by the negative reference, so time t₂ is variable and dependent on the value of voltage accumulated on capacitor C during time t₁. This voltage, of course, was determined by the value of analog input voltage. Since time t₂ is dependent on the value of analog input voltage, the number of counts registered in the counter will also be a function of the analog input voltage.

Figure 8.15 contrasts the results of two different analog input voltages. V_C1 is the result of a higher input voltage. It takes a certain amount of time (t₂) to discharge the capacitor and stop the counter. A lower input voltage (V_C2) charges C to a lower voltage during the fixed time period t₁, so the discharge time (t₃) is shorter and the counter will have a smaller count. The final converted result appears in the counter and ignores the MSB.

The dual-slope A/D conversion method is very popular in applications that do not require high-speed operation. It has distinct advantages that include high immunity to component tolerances, component drifts, and noise. This increased immunity stems from the fact that errors introduced during the positive slope will be largely offset by similar errors during the negative slope. The circuit offers total rejection of noise signals that are even multiples of the time period t₁, since the net effect of a full cycle of noise is 0.

Complete dual-slope converter systems are available in integrated form. A common application is for digital voltmeters. The analog portion of such a system is manufactured by National Semiconductor Corporation in the form of an LF12300 integrated circuit. Analog Devices has a patented improvement on the basic dual-slope converter called Quad-Slope conversion. This is used in the AD7550 13-bit A/D converter manufactured by Analog Devices.

Pet Sounds – Electronic synthesis

Introduction

The theory of electronic oscillators was covered in Chapter 5 . There we met several practical examples of LC-based oscillators and Wein-bridge types for the generation of sine-waves, astable multivibrators for the generation of square waves as well as ramp generators for the generation of sawtooth waveforms. We noted that each waveform had a different harmonic structure and, consequently, a different timbre when reproduced over loudspeakers. These circuits form the basis of analogue sound generation and synthesis. In many ways, Chapter 5 pre-empted some of the material which might have waited until here. For what is an electric organ if it is not a synthesised pipe organ? Later in the chapter, we will return to the subject of the emulation of real instruments, the oft misunderstood term for music synthesis. In the first half, I want to concentrate on the development of the analogue synthesiser which owes its genesis to Robert Moog, the inventor of the first commercial synthesiser and the artistic inspiration of the composers working in the early post-Second World War electronic music studios; composers of the stature of Stockhausen, Eimert and Berio. Analogue synthesisers contain certain cardinal circuit blocks each, originally, more at home in a laboratory than in a music studio! Each of these is now considered in turn.

A fourth generation of LCD backlight technology

Jim Williams , in Analog Circuit Design , 2013

Precision PWM generator

Figure F6 shows a simple circuit which generates precision variable pulse widths. This capability is useful when testing PWM-based intensity schemes. The circuit is basically a closed-loop pulse width modulator. The crystal controlled 1kHz input clocks the C1/Q1 ramp generator via the differentiator/CMOS inverter network and the LTC201 reset switch. C1’s output drives a CMOS inverter, the output of which is resistively sampled, averaged and presented to A1’s negative input. A1 compares this signal with a variable voltage from the potentiometer. A1’s output biases the pulse width modulator, closing a loop around it. The CMOS inverter’s purely ohmic output structure combines with A1’s ratiometric operation (e.g., both of A1’s input signals derive from the 5V supply) to hold pulse width constant. Variations in time, temperature and supply have essentially no effect. The potentiometer’s setting is the sole determinant of output pulse width. Additional inverters provide buffering and furnish the output. The Schottky diodes protect the output from latchup due to cable-induced ESD or accidental events 1 during testing.

Figure F6 . The Calibrated Pulse Width Test Box. A1 Controls C1-Based Pulse Width Modulator, Stabilizing Its Operating Point

The output width is calibrated by monitoring it with a counter while adjusting the 2kΩ trim pot.

As mentioned, the circuit is insensitive to power supply variation. However, the CCFL circuit averages the PWM output. It cannot distinguish between a duty cycle shift and supply variation. As such, the test box’s 5V supply should be trimmed ±0.01V. This simulates a “design centered” logic supply under actual operating conditions. Similarly, paralleling additional logic inverters to get lower output impedance should be avoided. In actual use, the CCFL dimming port will be driven from a single CMOS output, and its impedance characteristics must be accurately mimicked.

Test Equipment Principles

The time base and “X” amplifier

The time base provides the horizontal, or “X”, sweep, in a 1, 2, 5 sequence with a basic range of milliseconds per division to microseconds per division – better oscilloscopes range from 10 s per division to less than 1 ns per division. As with the “Y” amplifier, there is often a variable control that finely adjusts the horizontal scaling to make the waveform conveniently fit on the screen, but the horizontal sweep is now uncalibrated, so absolute time measurements are no longer possible.

The time base control adjusts the frequency of a precision ramp generator . Because the oscilloscope display tube uses electrostatic deflection plates to deflect the beam by an amount proportional to applied voltage, the combination of the two produces a sweep having horizontal deflection proportional to time.

Depending on the tube type and accelerating voltage (a higher voltage produces a brighter and more sharply focused display, but the faster electrons are harder to deflect), the deflection plates require ≈200 V_pk-pk to deflect the beam from one side of the tube face to the other. A dedicated high voltage “X” amplifier very similar to the “Y” amplifier is required to deliver the sweep voltages required by the tube.

If the sensitivity at the input of the “X” amplifier is made the same as that at the input of the “Y” amplifier, the “X” amplifier’s input can be switched to accept either the ramp from the time base generator, or Ch2 (leaving Ch1 to go to the “Y” amplifier). This is known as “XY” mode, and because it is so cheap to provide, all oscilloscopes offer it. “XY” mode allows the display of Lissajous figures – which are virtually useless, but were loved by producers of early “James Bond” films. See Figure 4.20 .

Figure 4.20 . A Lissajous figure showing a perfectly straight line (rather than this slight ellipse) would indicate zero phase error.

The previous Lissajous figure compared the voltage waveform across a choke with the current waveform through it. Because the phase between current and voltage is zero at resonance, and changes very sharply around it, testing phase is a very sensitive way of determining resonant frequency. When the two waveforms are perfectly in phase, the ellipse changes to a straight line, and this powerful example is the sole reason for elevating the modern status of Lissajous figures to virtually useless.

Fundamental Theories and Mechanisms of Failure

(i) σ(w) relation from uniaxial tests on panels

Cornelissen et al. (1986) perhaps have performed the best tensile test that ensures that the end platens, to which the specimen is glued ( Figure 16 ), remain parallel throughout the test. This is achieved by connecting a guiding system provided with ball bushings to the loading (movable) platen, and by correcting the load readings for the (low) friction of this system. The closed loop servo-hydraulic loading machine is controlled at a deformation rate of ∼0.08 μm s −1 . Deformation of double-edge notched specimens was measured by a pair of LVDTs straddling the unnotched ligament. The signals for the LVDTs were averaged, and the average signal compared with the signal from a specially designed ramp generator to eliminate noise.

Figure 16 . A schematic illustration of closed loop uniaxial testing system.

To confirm the accuracy of σ(w) curves measured from static tensile tests, envelope curves under repeated and alternating loading in the postpeak region were also recorded and compared with the static curves. These envelope curves were found to be practically coincident with the static test results. The broken lines in Figure 17 represent a normal density concrete (NC) with density 2,370 kg m −3 , compressive strength f c ′ = 47 MPa , E=39 GPa, and f t ′ = 3.2 MPa , whereas the solid lines represent a lightweight concrete (LC) with density 1,865 kg m −3 , f c ′ = 49 MPa , E=22.4 GPa, and f t ′ = 2.43 MPa . The designations a, b, c, and d stand for static tensile test, and postpeak cyclic tests when the load was reduced to 10%, −15%, and −100% of f t ′ , respectively.

Figure 17 . Envelope curves for NC and LC from test types a to d.

The curves in Figure 17 are the stress against the total deformation (w_t). In order to determine σ(w) relations, it is necessary to deduct the elastic and any prepeak inelastic deformation from w_t. The amount of deformation to be deducted can be obtained by drawing a line from the peak stress parallel to the initial loading curve, as illustrated in Figure 18 .

Figure 18 . Stress-crack opening relations for NC and LC. Open circles are test results and solid lines σ(w) regression relations (9)–(10) .

Cornelissen et al. (1986) performed a regression analysis of the measured net inelastic deformations in the postpeak regime (open circles in Figure 18 ) and found the best-fit (standard deviation≈0.06) curves to be

with the optimum values of w_c, C₁, and C₂, as shown in the respective figures for NC and LC mixes. The “critical” crack opening displacement was identified with complete loss of capacity to transfer normal stress (σ).

Power Supplies

20.5.5 Control Circuits and Pulse-Width Modulation

In previous subsections, we presented several popular voltage regulators that may be used in a switching mode power supply. This section discusses the control circuits that regulate the output voltage of a switching regulator by constantly adjusting the conduction period t_on or duty cycle d of the power switch. Such adjustment is called pulse-width modulation (PWM).

The duty cycle is defined as the fraction of the period during which the switch is on, that is,

where T is the switching period, that is, t off = T − t on . By adjusting either t_on or t_off or both, d can be modulated. Thus, PWM controlled regulators can operate at variable frequency and fixed frequency.

Among all types of PWM controllers, the fixed-frequency controller is by far the most popular choice. There are two main reasons for their popularity. First, low-cost fixed-frequency PWM IC controllers have been developed by various solid-state device manufacturers, and most of these IC controllers have all the features that are needed to build a PWM switching power supply using a minimum number of components. Second, because of their fixed-frequency nature, fixed-frequency controllers do not have the problem of unpredictable noise spectrum associated with variable frequency controllers. This makes EMI control much easier.

There are two types of fixed-frequency PWM controllers, namely, the voltage-mode controller and the current-mode controller . In its simplified form, a voltage-mode controller consists of four main functional components: an adjustable clock for setting the switching frequency, an output voltage error amplifier for detecting deviation of the output from the nominal value, a ramp generator for providing a sawtooth signal that is synchronized to the clock, and a comparator that compares the output error signal with the sawtooth signal. The output of the comparator is the signal that drives the controlled switch. Fig. 20.28 shows a simplified PWM voltage-mode controlled forward regulator operating at fixed frequency and its associated driving signal waveform. As shown, the duration of the on-time t_on is determined by the time between the reset of the ramp generator and the intersection of the error voltage with the positive-going ramp signal.

Fig. 20.28 . A simplified voltage-mode controlled forward regulator: (A) circuit and (B) the associated driving signal waveform.

The error voltage v_e is given by

From Eq. (20.84) , the small-signal term can be separated from the dc operating point by

The dc operating point is given by

Inspecting the waveform of the sawtooth and the error voltage shows that the duty cycle is related to the error voltage by

where V_p is the peak voltage of the sawtooth.

Hence, the small-signal duty cycle is related to the small-signal error voltage by

The operation of the fixed-frequency voltage-mode controller can be explained as follows. When the output is lower than the nominal dc value, a high error voltage is produced. This means that Δv_e is positive. Hence, Δd is positive. The duty cycle is increased to cause a subsequent increase in output voltage. The feedback dynamics (stability and transient response) is determined by the operational amplifier circuit that consists of Z₁ and Z₂. Some of the popular voltage-mode control ICs are SG1524/25/26/27, TL494/5, and MC34060/63.

The current-mode control makes use of the current information in a regulator to achieve output voltage regulation. In its simplest form, current-mode control consists of an inner loop that samples the inductance current value and turns the switches off as soon as the current reaches a certain value set by the outer voltage loop. In this way, the current-mode control achieves faster response than the voltage mode. There are two types of fixed-frequency PWM current-mode control, namely, the peak current-mode control and the average current-mode control.

In the peak current-mode control, no sawtooth generator is needed. In fact, the inductance current waveform is itself a sawtooth. The voltage analog of the current may be provided by a small resistance or by a current transformer. Also, in practice, the switch current is used since only the positive-going portion of the inductance current waveform is required. Fig. 20.29 shows a peak current-mode controlled flyback regulator.

Fig. 20.29 . A simplified peak current-mode controlled flyback regulator: (A) circuit and (B) the associated waveforms.

In Fig. 20.29 , the regulator operates at fixed frequency. Turn-on is synchronized with the clock pulse, and turnoff is determined by the instant at which the input current equals the error voltage V_e.

Because of its inherent peak current-limiting capability, the peak current-mode control can enhance reliability of power switches. The dynamic performance is improved because of the use of the additional current information. One main disadvantage of the peak current-mode control is that it is extremely susceptible to noise, since the current ramp is usually small compared with the reference signal. A second disadvantage is its inherent instability property at duty cycle exceeding 50%, which results in subharmonic oscillation. Typically, a compensating ramp is required at the comparator input to eliminate this instability. The third disadvantage is that it has a nonideal loop response because of the use of the peak, instead of the average current sensing.

Fig. 20.30 shows an average current-mode controlled flyback regulator. In the circuit, a PWM modulator (instead of a clocked SR latch in the peak current-mode control) is employed to compare the current error with an externally generated sawtooth signal to formulate the desired control signal. The main advantages of this method over the peak current control are that it has excellent noise immunity property, it is stable at duty cycle exceeding 50%, and it provides good tracking of average current. However, since there are three compensation networks (Z₁, Z₂, and Z₃), the analysis and optimal design of these networks are nontrivial. This is a major obstacle for adopting the average current-mode control.

Fig. 20.30 . A simplified average current-mode controlled flyback regulator: (A) circuit and (B) the associated waveforms.

It should be noted that current-mode control is particularly effective for the flyback and boost-type regulators that have an inherent right-half-plane zero. Current-mode control effectively reduces the system to first order by forcing the inductor current to be related to the output voltage, thus achieving faster response. In the case of the buck-type regulator, current-mode control presents no significant advantage because the current information can be derived from the output voltage, and hence, faster response can still be achieved with a proper feedback network. Some of the popular current-mode control ICs are UC3840/2, UC3825, MC34129, and MC34065.

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