Ripple carry adder что это

Where Boolean logic has 2 2 = 4 unary operators, the addition of a third value in ternary logic leads to a total of 3 3 = 27 distinct operators on a single input value. Similarly, where Boolean logic has 2 2 2 = 16 distinct binary operators (operators with 2 inputs), ternary logic has 3 3 2 = 19,683 such operators. Where we can easily name a significant fraction of the Boolean operators (not, and, or, nand, nor, exclusive or, equivalence, implication), it is unreasonable to attempt to name all but a small fraction of the possible ternary operators.

Advantages of Ternary Logic

A ternary logic representation enables a more compact and efficient information encoding than the equivalent binary logic representation. The argument stated is as follows: if we assume that a digital circuit has N possible input combinations, then a binary circuit requires log₂N input lines and a ternary circuit requires log₃N input lines.

Therefore, a ternary encoded realization of a given binary logic function should require 0.63 times the input lines than the corresponding binary realization.

Disadvantages of Ternary Logic

Although ternary logic circuits should require fewer input lines than the equivalent binary logic circuits, ternary logic circuits are currently not a practical choice. The reasons are

1. Ternary hardware implementation technology is still in the theoretical, simulation, and laboratory test levels
2. Representing three ternary logic levels (0, 1, and 2) using voltage levels of existing technology is not yet effectively defined
3. No computational model and programming language is developed. However, simulating results of ternary circuit implementation using complementary metal oxide semiconductor (CMOS), resonant tunneling diode (RTD), and carbon nano-tube technologies, demonstrating that ternary logic may be a choice for future computing.

Various possible representations for the ternary system

More about the balanced Ternary Numbering System

Today, mostly all hardware is designed for binary computing. If we had a stable electronic component with three stable states, the world perhaps would have turned to ternary computing. However, this is not the truth today. The balanced ternary radix notation has some beneficial properties:

1. Ternary inversion is easy, just exchange −1 with 1 and vice versa. If we use an example, 24 is represented as 1T0, and -24 as T10 in balanced ternary notation (T is simply a notation for -1). This is simpler than the rule for the two’s complement in binary logic.
2. The sign of a number is given by its most significant nonzero ’trit’
3. The operation of rounding to the nearest integer is identical to truncation.
4. Addition and subtraction are essentially the same operation (I.e. you merely add the digits using the rules for addition of digits)

Ternary Arithmetics

Ternary arithmetic can offer a more compact notation than binary arithmetic, and would have been an obvious choice if the hardware manufacturers would have found a ternary switch.

Balanced Ternary Addition and Multiplication

Examples:

Ternary combinational circuits (Ternary gates)

A combinational circuit consists of input variables, ternary logic gates and output variables. The output of the circuit depends only upon the present input. Logic gates accept signals from the input variables and generate output signals. This process transforms ternary information from
the given input data to the required ternary output data.

As mentioned above we can easily name a significant fraction of the Boolean operators (not, and, or, nand, nor, exclusive or, equivalence, implication), however, it is unreasonable to attempt to name all but a small fraction of the possible ternary operators. We will consider the following ternary circuits:

And (Min): It is natural to extend the Boolean and function to a ternary function by declaring that the result is true only if both inputs are true, false if any input is false, and unknown otherwise.

Or (Max): It is also natural to extend the Boolean or function to ternary by declaring that the result is true if any input is true, false only if both inputs are false, and unknown otherwise.

Consensus: In Boolean logic, the inverse of exclusive or is true when the two inputs are the same, and false when they are different. There are several natural extensions of this idea to ternary logic. One of them is the logical consensus of a set of variables, which is true if all are true, false if all are false, and otherwise unknown

Any: Where consensus requires that both inputs agree before it asserts anything but unknown, the accept anything operator declares an unknown conclusion only if both inputs are unknown or actively disagree. Otherwise, it jumps to a conclusion from any non-unknown input available to it.

Increment and Decrement: In Boolean logic, the inverter may be thought of as incrementing or decrementing its argument modulo 2. In ternary logic, the modulo 3 increment and decrement functions are quite distinct from inversion.

Synthesis, Minimization and Realization for Ternary Functions

Relationships interrelated in the ternary logic system

A ternary logic function can be represented as a Max-Min expression. Ternary Max-Min expressions are defined as follows:
Variable: Any symbol that takes value from the set T ∈ <0,1,2>is a ternary variable.
Literal: Literals are transformed forms of a variable. They are used to form Max-Min expressions.

In the literature two types of literals are commonly used: 1-reduced Post literals and 2-reduced post literals. A 1-reduced Post literal of a variable x is represented as x_i, where i ∈ <0,1,2>. When x = i, then x_i = 1, otherwise x_i = 0. The 1-reduced Post literals of a variable is shown below.

A 2-reduced Post literal of a variable x is represented as x_i, where i ∈ <0,1,2>. When x = i, then x_i = 2, otherwise x_i = 0. The 2-reduced Post literals of a variable is shown below. This example makes use of different sets of literals to form Max-Min expressions as discussed previously.

Minterm: When literals of variables of a function are combined using the Min operation, then the term is called a minterm. For example, for a 3-variable ternary logic function F(x,y,z), xyz and xz are two examples of minterms.

Max-Min Expression: When two or more minterms are combined using Max operations, then the expression is called a Max of minterms (Max-Min) expression. For example, for a 3-variable ternary logic function F(x,y,z) = xy + yz + xyz is an example of a Max-Min expression.

Any function F(x,y,z) can always be represented as

Three basic methods to minimize ternary functions are:

1. Manipulation of algebra expression as in Boolean algebra.
2. The tabular method.
3. Ternary K. map method.
   For the implementation of ternary circuits it is necessary to convert ternary variable into unary variable (using the 2-Reduced Post Literals table).

Ternary half adder

A circuit for the addition two 1 trit numbers is referred to as a half adder. the circuit does not consider a carry generated in the previous addition. The addition process in ternary logic system is shown below. Here A and B are two inputs and sum(S) and carry (CARRY)
are two outputs.

Analysis

A karnaugh map (K-map) is used to represent the sum and carry output. K-maps are useful for minimization and optimization of logic circuits. Here a K-map of 2 inputs is used. Since no grouping of 2’s and 1’is possible, the output equation is as below.

Implementation

Ternary full adder

As with half adders, one stage of a ternary full adder can be described by a numerical table giving the sum SUM and carry out CARRY as a function of the three inputs A, B, along with the carry in C:

Analysis

A karnaugh map (K-map) is used to represent the sum and carry output. K-maps are useful for minimization and optimization of logic circuits. Here a K-map of 3 inputs is used.

Implementation

Ternary Full Subtractor

Ternary full-Subtractor is a circuit that subtracts two inputs and previous borrow. Truth table for Subtractor is shown below

Ternary Ripple Carry Adder

Ripple-carry adder(RCA) is a well-known circuit for performing addition of two numbers by cascading ternary full adders. A Ternary RCA is quite similar to its Binary counterpart. A Ternary Half Adder is employed to add the least significant Ternary digits. The rest are summed up by Ternary Full Adders. As mentioned before, Ternary Full Adder adds three Ternary input variables.

Implementation

Ternary Comparators

Ternary comparator circuit camper two inputs X₁, X₂ and accordingly generates output as X₁ = X₂, X₁ > X₂, X₁ Analysis and Implementation

Ternary Multiplier

Ternary multiplier is a circuit that multiplies two input numbers and generates corresponding product. Truth table for this circuit is shown below:

The resulting expression for the product and carry are shown:

The corresponding K-maps are shown:

Ternary Multiplexers and Demultiplexers

Multiplexer is a circuit having multiple inputs and a single output. It is also known as decoder. The output function of the multiplexer is determined by the number of function lines. Thus for 2 trit
multiplexer the output will be 3 2 = 9 and two will be the function select lines. Multiplexer i.e. function
selection logic selects 1 out of 9 functions as an output. Function select logic is implemented using logic gates. The output equation of function selection logic is:

Demultiplexer is also referred to as encoder. Its functionality is reverse to that of multiplexer. It accepts the single input and distributes it over several outputs

Simple Ternary D Latch

Although design of circuits implementing combinational ternary logic is straightforward, the design of a simple and robust ternary memory element (i.e latch) suitable for integrated circuit (IC) implementation has been challenging. However, a simple ternary latch can be obtained by replacing the binary NOR or NAND gates used with corresponding ternary T_NOR or T_NAND gates.

Simple Ternary D Flip-Flap-Flop

The Master Slave (MS) ternary D Flip-Flap-Flop (FFF) is realized based on the ternary D latches. This is similar to the way the binary D Flip-Flop (FF) is realized using binary D latches. The logic diagram and the operation description of the MS binary D flip-flop are well known. In order to implement the MS ternary D FFF , we replace the binary D latches with ternary D latches (realized with ternary negated-minimun gates of two inputs – NAND) and the binary inverters with simple ternary inverters (STI). The truth tables for both the ternary NAND circuits and ternary STI circuits are shown

For MS ternary D FFF with binary clock, the data are ternary (0, 1 and 2 logic) and the clock is binary (low and high – in our
implementation, 0 and 2 logic). The MS ternary D FFF with
binary clock can read the data when the clock goes from low to
high (positive edge) or from high to low (negative edge), depending
on the number of STIs.

The inputs of the ternary D FFF are Data and Clk, and the outputs are Q and Not_Q. The clock signal is binary and the logic levels are denoted 0 and 2, in order to maintain the correspondence with electrical implementation

1-bit Ternary Arithmetic and Logic Unit (T-ALU)

Ternary Arithmetic Logic Unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It represents the fundamental building block of the Central Processing Unit (CPU) of a ternary computer. ALU carries out arithmetic operations like addition, subtraction, multiplication, and logic operations compare, NAND, NOR, NOT, AND, and OR. Below is shown a primitive architecture of a 1 trit ALU

Basic building blocks of ALU are decoders, function select logic (Multiplexer), transmission gate and separate processing modules. Function selection logic selects 1 out of 9 functions listed depending upon the logic state on function select lines W and Z.

Output lines of selection logic are connected to TG (Ternary gate) associated with each module. Any module is selected only when associated TG is enabled else it is isolated from data lines. For e.g. If input from select lines W and Z = 0, output E₀ of selection logic is high (2) while E₁, to E₈ is low (0) so, TG associated with adder module will be enable allowing data
lines to be connected to adder modules while other modules are isolated from the data lines.

Finally, by cascading n/2 trit ALU slices, an n trit ALU can be formed.

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